FIG. 1 shows an embodiment of a computing system (e.g., a computer). The computer includes processing cores 101_1 to 101_N. Each processing core includes at least one instruction execution pipeline to execution instructions. The processing cores 101_1 to 101_N communicate to one another and a memory controller 102 through an interconnection network 103. A graphics processor 104 can be coupled to the interconnection network 103 or the memory controller 102 directly. Likewise, an I/O hub 105 can be coupled to the interconnection network 103 or the memory controller 102, directly. The memory controller is coupled to a system memory 106.
In operation, any one of the processing cores 101_1 to 101_N can invoke system memory 106 to store the instructions of the various software programs that the processing cores 101_1 to 101_N execute as well as the specific data that the software programs operate on. With the instructions and data being kept in system memory 106, the processing cores 101_1 to 101_N will need to access system memory 106 in order to fetch the same at appropriate times. Moreover, as the software programs operate on data they may likewise change existing data or create new data that is ultimately written into system memory 106. Here, multiple caching levels may reside between a processing core's instruction execution pipeline(s) and system memory 106. A typical memory access sequence therefor includes snooping the various levels of cache for a valid cache line having the targeted system memory address. If no such cache line is found after a last level cache 107 is snooped, a memory access request is issued from the last level cache 107 to the memory controller 102.
A single “processor” may include the multiple processing cores 101_1 to 101_N and any/all of the other components depicted in FIG. 1 in various combinations. Multiple such processors may be coupled together (e.g., through an extension of network 103) to form a single computing system (here the system memory of each processor holds a “slice” of the total system memory address space).
FIG. 2a shows a typical prior art process to provide instructions or data to a processing core from system memory. As observed in FIG. 2a the processing core is viewed as a “requestor” that issues a request 201 to a memory controller. Alternatively, the request may first progress through various levels of cache until each snooped cache has resulted in a miss requiring the request to proceed to the memory controller. The request includes a tag and a system memory address. The memory controller receives the request and ultimately performs a read into system memory 202 specifying the address in the request as the address for the read operation. After the memory responds with the requested information, the memory controller sends a response 203 back to the processor that includes the requested information and the tag that was included in the original request. With the tag, the processor is able to correlate the received information as the information retrieved from the address specified in the original request. Note that the process of FIG. 2a is used to fetch both software instructions and data.
FIG. 2b shows a typical prior art process to write information from a processor into system memory. Again the processor is viewed as a requestor that issues a request 204 to a memory controller. The request includes a tag, a system memory address and the information to be written. The memory controller receives the request and ultimately performs a write into system memory 205 where the information received with the request is written into system at the address that was also included in the request. Upon a successful write operation into system memory, the memory controller sends a response to the processor 206 that includes the tag included in the original request and an acknowledgement that the write was successful. Here, whether or not an acknowledgement is sent upon a successful write is memory interfaces dependent. Some memory interfaces support such an acknowledgement while others do not.